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RDC-19220/2/4 SERIES
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(R)
16-BIT MONOLITHIC TRACKING RESOLVER (LVDT)-TO-DIGITAL CONVERTERS
FEATURES
* +5 Volt Only Option * Only Five External Passive Components * Programmable: - Resolution: 10-, 12-, 14-, or 16-Bit - Bandwidth: to 1200 Hz - Tracking: to 2300 RPS * Differential Resolver and LVDT Input Modes * Velocity Output Eliminates Tachometer * Built-In-Test (BIT) Output * No 180 Hang-Up
DESCRIPTION
The RDC-19220 Series of converters are low-cost, versatile, 16-bit monolithic, state-of-the-art Resolver(/LVDT)-to-Digital Converters. These single-chip converters are available in small 40-pin DDIP, 44pin J-Lead, and 44-pin MQFP packages and offer programmable features such as resolution, bandwidth and velocity output scaling. Resolution programming allows selection of 10-, 12-, 14-, or 16-bit, with accuracies to 2.3 min. This feature combines the high tracking rate of a 10-bit converter with the precision and low-speed velocity resolution of a 16-bit converter in one package. The velocity output (VEL) from the RDC-19220 Series, which can be used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only option) referenced to ground with a linearity of 0.75% of output voltage. The full scale value of VEL is set by the user with a single resistor. RDC-19220 Series converters are available with operating temperature ranges of 0 to +70C, -40 to +85C and -55 to +125C. Military processing is available.
* Small Size: Available in DDIP PLCC or , MQFP Packages * -55 to +125C Operating Temperature Available * Programmable for LVDT input
APPLICATIONS
With its low cost, small size, high accuracy and versatile performance, the RDC-19220 Series converter is ideal for use in modern high-performance industrial and military control systems. Typical applications include motor control, radar antenna positioning, machine tool control, robotics, and process control. MIL-PRF-38534 processing is available for military applications.
FOR MORE INFORMATION CONTACT:
Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
Technical Support: 1-800-DDC-5757 ext. 7771
(c)
1999 Data Device Corporation
Data Device Corporation www.ddc-web.com
+REF -REF BIT -VSUM C BW R1 GAIN DEMODULATOR C BW 10 RB VEL CONTROL TRANSFORMER HYSTERESIS AB -VCO RS 16 BIT UP/DOWN COUNTER E DATA LATCH VCO & TIMING INTEGRATOR RV RC EM BIT 1 EL THRU BIT 16 A B CB
SIN -S
-
+S
+
COS
-C
-
+C
+
2
+5C +CAP -CAP -5C
-5 V INVERTER
A GND +5 V GND -5 V
INH
RDC-19220 SERIES R-12/05-0
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
TABLE 1. RDC-19220 SERIES SPECIFICATIONS
These specifications apply over the rated power supply, temperature and reference frequency ranges, and 10% signal amplitude variation and harmonic distortion. PARAMETER RESOLUTION ACCURACY REPEATABILITY DIFFERENTIAL LINEARITY REFERENCE Type Voltage: differential single ended overload Frequency Input Impedance SIGNAL INPUT Type Voltage: operating overload Input impedance DIGITAL INPUT/OUTPUT Logic Type Inputs UNIT Bits Min LSB LSB VALUE 10, 12, 14, or 16 4 or 2 + 1 LSB (note 3) 1 max 1 max in the 16th bit (+REF, -REF) Differential 10 max 5 max 25 continuous, 100 transient DC to 40,000 (note 4 & note 9) 10M min // 20 pf
TABLE 1. RDC-19220 SERIES SPECS (CONT'D)
These specifications apply over the rated power supply, temperature and reference frequency ranges, and 10% signal amplitude variation and harmonic distortion. PARAMETER DYNAMIC CHARACTERISTICS Resolution Tracking Rate (max)(note 4) Bandwidth(Closed Loop) (max) (note 4) Ka (Note 7) A1 A2 A B Acceleration (1 LSB lag) Settling Time(179 step) VELOCITY CHARACTERISTICS Polarity Voltage Range(Full Scale) Scale Factor Error Scale Factor TC Reversal Error Linearity Zero Offset Zero Offset TC Load Noise POWER SUPPLIES Nominal Voltage Voltage Range Max Volt. w/o Damage Current TEMPERATURE RANGE Operating (Case) -30X -20X -10X -A0X Storage plastic package ceramic package MOISTURE SENSITIVITY LEVEL MQFP RDC-19224 THERMAL RESISTANCE Junction-to-Case (jc) 40-pin DDIP (ceramic) 44-pin J-Lead (ceramic) PHYSICAL CHARACTERISTICS Size: 40-pin DDIP 44-pin J-Lead 44-pin MQFP Weight: 40-pin DDIP 44-pin J-Lead 44-pin MQFP UNIT VALUE (at maximum bandwidth) bits rps Hz 1/sec2 1/sec 1/sec 1/sec 1/sec deg/s2 msec 10 1152 1200 5.7M 19.5 295k 2400 1200 2M 2 12 288 1200 5.7M 19.5 295k 2400 1200 500k 8 14 72 600 1.4M 4.9 295k 1200 600 30k 20 16 18 300 360k 1.2 295k 600 300 2k 50
VP-P VP V Hz Ohm
(+S, -S, SIN, +C, -C, COS) Resolver, differential, groundbased Vrms 2 15% V 25 continuous Ohm 10M min//10 pf. (Note 6) TTL/CMOS compatible Logic 0 = 0.8 V max. Logic 1 = 2.0 V min. Loading =10 A max pull-up current source to +5 V //5 pF max. CMOS transient protected Logic 0 inhibits; Data stable within 0.3 s Logic 0 enables;Data stable with -in 150 ns (logic 0=Transparent) Logic 1 = High Impedance Data High Z within 100 nS Mode B resolver 0 " 0 " 1 " 1 LVDT -5 V " 0 " 1 " -5 V A Resolution 0 10 bits 1 12 bits 0 14 bits 1 16 bits 0 8 bits -5 V 10 bits -5 V 12 bits -5 V 14 bits
V % PPM/C % % mv V/C k (Vp/V)% V % V mA
Positive for increasing angle 4 (at nominal ps) 10 typ 20 max 100 typ 200 max 0.75 typ 1.3 max 0.25 typ 0.50 max 5 typ 10 max 15 typ 30max 8 min 1 typ . 125 min 2 max (note 5) +5 -5 5 5 +7 -7 14 typ, 22 max (each)
Inhibit (INH) Enable Bits 1 to 8 (EM) Enable Bits 9 to 16 (EL)
Resolution and Mode Control (A & B) (see notes 1 and 2. pre-set to logic 1 note 6)
C C C C C C
0 to +70 -40 to +85 -55 to +125 -40 to +125 -65 to +150 -65 to +150
Outputs Parallel Data (1-16)
JEDEC 2
Converter Busy (CB)
Zero Index (Zl) Built-in-Test (BIT)
Drive Capability
10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see TABLE 2) 0.25 to 0.75 s positive pulse leading edge initiates counter update. Logic 1 at all 0s (ENL to -5 V); LSBs are enabled Logic 0 for BIT condition. 100 LSBs of error typ. with a filter of 500 S, or total Loss-ofSignal (LOS) 50 pF + Logic 0; 1 TTL load, 1.6 mA at 0.4 V max Logic 1; 10 TTL loads, = 0.4 mA at 2.8 V min Logic 0; 100 mV max driving CMOS Logic 1; +5 V supply minus 100mV min driving CMOS, High Z; 10 uA//5 pF max
C/W C/W
4.6 2.4
in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08) in(mm) 0.690 square (17.526) in(mm) 0.394 square (10.0) Plastic n/a n/a 0.017 (0.5) Ceramic 0.24 (6.80) 0.065 (1.84) n/a
oz(g) oz(g) oz(g)
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3
RDC-19220 SERIES R-12/05-0
Notes for TABLE 1:(from previous page) 1. Unused data bits are set to logic "0." 2. In LVDT mode, bit 16 is LSB for 14-bit resolution or bit 12 is LSB for 10-bit resolution. 3. Accuracy spec below for LVDT mode, null to + full scale travel (45 degrees).(2 wire-LVDT configuration). 4 Min part = 0.15% + 1 LSB of full scale "resolution set". 2 Min part = 0.07% + 1 LSB of full scale "resolution set" Accuracy spec below for LVDT mode, null to + full scale travel (90 degrees).(3 wire-LVDT configuration). 4 Min part = 0.07% + 1 LSB of full scale "resolution set". 2 Min part = 0.035% + 1 LSB of full scale "resolution set" Note that this is the converter spec only and does not consider the front end external resistor tolerances. 4. See text, General Setup Considerations and HigherTracking Rates. 5. See text: General Setup Considerations for RDC19222. 6. Any unused input pins may be left floating (unconnected). All input pins are internally pulled-up to +5 Volts. 7. Ka = Acceleration constant, for a full definition see the RD/RDC application manual acceleration lag section. 8. When using internally generated -5V, the internal -5V charge pump when measured at the converter pin, can read as low as -20% (or 4V). 9. No 180 hangup with A/C reference.
. Its output is an analog error angle, or difference angle, between the two inputs. The CT performs the ratiometric trigonometric computation of SINCOS - COSSIN = SIN(-) using amplifiers, switches, logic and capacitors in precision ratios. Note: The transfer function of the CT is normally trigonometric, but in LDVT mode the transfer function is triangular (linear) and could thereby convert any linear transducer output.
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT 1(MSB) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DEG/BIT 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 MIN/BIT 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33
THEORY OF OPERATION
The RDC-19220 Series of converters are single CMOS custom monolithic chips. They are implemented using the latest IC technology which merges precision analog circuitry with digital logic to form a complete, high-performance tracking Resolver-toDigital converter. For user flexibility and convenience, the converter bandwidth, dynamics and velocity scaling are externally set with passive components. FIGURE 1 is the functional block diagram of the RDC-19220 Series. The converter operates with 5 Vdc power supplies. Analog signals are referenced to analog ground, which is at ground potential. The converter is made up of two main sections; a converter and a digital interface. The converter front-end consists of sine and cosine differential input amplifiers. These inputs are protected to 25 V with 2 k resistors and diode clamps to the 5 Vdc supplies. These amplifiers feed the high accuracy Control Transformer (CT). Its other input is the 16-bit digital angle
RB CBW
Note: EM enables the MSBs and EL enables the LSBs.
The converter accuracy is limited by the precision of the computing elements in the CT. For enhanced accuracy, the CT in these converters uses capacitors in precision ratios, instead of the more conventional precision resistor ratios. Capacitors, used as computing elements with op-amps, need to be sampled to eliminate voltage drifting. Therefore, the circuits are sampled at a high rate (67 kHz) to eliminate this drifting and at the same time to cancel out the op-amp offsets. The error processing is performed using the industry standard technique for type II tracking R/D converters. The dc error is integrated yielding a velocity voltage which in turn drives a voltage controlled oscillator (VCO). This VCO is an incremental integrator (constant voltage input to position rate output) which togethVEL
C BW /10 RS -VSUM
RV
VEL
-VCO 50 pf C VCO
CT RESOLVER INPUT () + GAIN DEMOD
R1 VCO 1 CS F S 11 mV/LSB 1.25 V THRESHOLD
-
16 BIT UP/DOWN COUNTER
H=1
DIGITAL OUTPUT ()
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
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er with the velocity integrator forms a type II servo feedback loop. A lead in the frequency response is introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. The settings of the various error processor gains and break frequencies are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user.
GENERAL SETUP CONSIDERATIONS
Note: For detailed application and technical information see the RD/RDC converter applications manual which is available for download from the DDC web site @ www.ddc-web.com.
DDC has external component selection software which considers all the criteria below, and in a simple fashion, asks the key parameters (carrier frequency, resolution, bandwidth, and tracking rate) to derive the external component value. The following recommendations should be considered when installing the RDC-19220 Series R/D converters: 1) In setting the bandwidth (BW) and Tracking Rate (TR) (selecting five external components), the system requirements need to be considered. For greatest noise immunity, select the minimum BW and TR the system will allow. 2) +5 and -5 volt operation: Power supplies are 5 V dc. For lowest noise performance it is recommended that a 0.1 F or larger cap be connected from each supply to ground near the converter package. When using a +5V and -5V supply to power the converter, RDC-19222 pins 22, 23, 25, 26 must be no connection, and on RDC-19224 pins 20, 40, 16, 11, must be no connection. Also, the 10uF cap is not connected to +cap and -cap pins. 3) This converter has 2 internal ground planes, which reduce noise to the analog input due to digital ground currents. The resolver inputs and velocity output are referenced to AGND. The digital outputs and inputs are referenced to GND. The AGND and GND pins must be tied together as close to the converter package as possible. Not shorting these pins together as close to the converter package as possible will cause unstable converter results.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from its Transfer Function Block Diagrams and its Bode Plots (open and closed loop). These are shown in FIGURES 2, 3, and 4. The open loop transfer function is as follows:
A2 S +1 B Open Loop Transfer Function = S2 S +1 10B
( (
) )
where A is the gain coefficient and A2= A1A2 and B is the frequency of lead compensation. The components of gain coefficient are error gradient, integrator gain and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod with 2 Vrms input) - Integrator Gain = Cs Fs volts per second per volt 1.1 CBW - VCO Gain = 1 LSBs per second per volt 1.25 RV CVCO
where: Cs = 10 pF Fs = 67 kHz when Rs = 30 k Fs = 100 kHz when Rs = 20 k Fs = 134 kHz when Rs = 15 k CVCO = 50 pF
RV, RB, and CBW are selected by the user to set velocity scaling and bandwidth.
-1 2d
GAIN = 4
b/o ct
(CRITICALLY DAMPED)
ERROR PROCESSOR RESOLVER INPUT () + CT e
A1 S + 1 B S S +1 10B
VELOCITY OUT VCO A2 S DIGITAL POSITION OUT ()
2A OPEN LOOP B A
-6 db
(rad/sec) 10B
/oc t
(B = A/2)
GAIN = 0.4
f BW = BW (Hz) =
2A
H=1
CLOSED LOOP
2A
2 2A
(rad/sec)
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
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FIGURE 4. BODE PLOTS
RDC-19220 SERIES R-12/05-0
4) The BIT output which is active low is activated by an error of approximately 100 LSBs. During normal operation for step inputs or on power up, a large error can exist.
-CAP
5) This device has several high impedance amplifier inputs (+C, -C, +S, -S, -VCO and -VSUM). These nodes are sensitive to noise and coupling components should be connected as close as possible. 6) Setup of bandwidth and velocity scaling for the optimized critically damped case should proceed as follows:
- Select the desired f BW (closed loop) based on overall system dynamics. - Select f carrier 3.5f BW - Select the applications tracking rate (in accordance with TABLE 3), and use appropriate values for R SET and R CLK - Compute Rv = Full Scale Velocity Voltage Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V 3.2 x Fs (Hz) x 108 Rv x (f BW)2
RDC-19222/4
+CAP
10uF
(-5c)
-5V
(+5c) +5V
.01uF
.01uF + + 47uF 47uF
FIGURE 5. -5V BUILT-IN INVERTER
7) Selecting a fBW that is too low relative to the maximum application tracking rate can create a spin-around condition in which the converter never settles. The relationship to insure against spin-around is as follows (TABLE 3): 8) For RDC-19222 & RDC-19224; package's only. This version is capable of +5V only operation. It accomplishes this with a charge pump technique that inverts the +5V supply for use as -5V, hence the +5V supply current doubles. The built-in -5 V inverter can be used by connecting pin 2 to 26, pin 17 to 22, a 10 F/10 Vdc capacitor from pin 23 (negative terminal) to pin 25 (positive terminal), and a 47 F/10 Vdc capacitor from -5 V to GND. The current drain from the +5 V supply doubles. No external -5 V supply is needed (SEE FIGURE 5). When using the -5 V inverter, the max. tracking rate should be scaled for a velocity output of 3.5 V max. Use the following equation to determine tracking rate used in the formula on page 5: TR (required) x (4.0) = Tracking rate used in calculation (3.5) Note: When using the highest BW and Tracking Rates, using the -5 V inverter is not recommended.
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 K 100 kHz for R CLK = 20 K 125 kHz for R CLK = 15 K - Compute RB = - Compute CBW 10 As an example: Calculate component values for a 16-bit converter with 100Hz bandwidth, a tracking rate of 10RPS and a full scale velocity of 4 volts. 4V = 97655 10 rps x 216 x 50 pF x 1.25 V 3.2 x 67 kHz x 108 = 21955 pF 97655 x 100 Hz2 0.9 CBW x f BW
- Rv =
- Compute CBW (pF) =
- Compute RB =
0.9 = 410 k 21955 x 10 -12 x 100 Hz
Note: DDC has software available to perform the previous calculations. Contact DDC to request software or visit our website at www.ddc-web.com to download software.
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW 1 0.45 0.25 0.125 RESOLUTION 10 12 14 16
HIGHER TRACKING RATES AND CARRIER FREQUENCIES
Tracking rate (nominally 4 V) is limited by two factors: velocity voltage saturation and maximum internal clock rate (nominally 1,333,333 Hz). An understanding of their interaction is essential to extending performance. The General Setup Considerations section makes note of the selection of Rv for the desired velocity scaling. Rv is the input resis-
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RDC-19220 SERIES R-12/05-0
bring it to 0 V. The output counts per second per volt input is therefore: 1 (Rv x 50 pF x 1.25) As an example: Calculate Rv for the maximum counting rate, at a VEL voltage of 4 V. For a 12-bit converter there are 212 or 4096 counts per rotation. 1,333,333/4096 = 325 rotations per second or 333,333 counts per second per volt.
Rv = 1 = 48 k (333,333 x 50 pF x 1.25)
TRANSFORMER ISOLATION
System requirements often include electrical isolation. There are transformers available for reference and synchro/resolver signal isolation. TABLE 6 includes a listing of the most common transformers. The synchro/resolver transformers reduce the voltage to 2 Vrms for a direct connection to the converter. See FIGURES 5A, 5B, 5C and 5D for transformer layouts and schematics, and FIGURE 6 for typical connections.
DC INPUTS
As noted in TABLE 1, the RD-19220/2/4 will accept DC inputs. * Operation from 0 to 180 or 180 to 359 only. This is due to the possibility of a unstable false null. IE: 180 hang-up. This 180 hang-up is unstable and once the converter moves it will go to the correct answer. In real world applications where an instantaneous 180 change are not possible the converter will always be correct within 360. The problem arises at power-up in real systems. If the converter angle powers up at exactly 180 from the applied input the converter will not move. This is very unlikely although it is theoretically possible. This condition is most often encountered during wrap around verification tests, simulations or troubleshooting. * Set the REF input to DC by tying RH to +5V and RL to GND or -5V. * Set the COS and SIN inputs such that max signal will be equal to 1.8VDC. IE: For 90, the SIN input will equal 1.8VDC. This will keep the BW hysteresis consistant with AC operation. * Input offsets will affect accuracy. Verify the COS and SIN inputs do not have DC offsets. If offsets are present , a differential op amp configuration can be used to minimize differential offset problems. * With DC inputs the converter BIT will remain at logic 0. * The Bandwidth value of the converter should be chosen based on the rate of change of the system's input amplitude variation, and should be large enough so to minimize it's effect on the system dynamics. Note that if the bandwidth is too high the system will be more susceptible to noise. * The accuracy of the converter using a DC input will be degraded from the rated accuracy. Consider the best case where the input is single ended and no additional DC offsets are present on the input converter - the accuracy will degrade by about 2 arc minutes. IE:, If a part is rated at 2 arc minutes, a DC input will degrade the accuracy to approximately 4 arc minutes.
The maximum rate capability of the RDC-19220 is set by Rs. When Rs = 30 k it is nominally 1,333,333 counts/sec, which equates to 325 rps (rotations per second). This is the absolute maximum rate; it is recommended to only run at <90% of this rate (as seen in TABLE 3), therefore the minimum Rv will be limited to 55 k. The converter maximum tracking rate can be increased 50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit modes by increasing the supply current from 12 to 15 mA (by using an Rc = 23 k), and by increasing the sampling rate by changing Rs to 20 k for 16- and 14-bit resolution or to 15 k for 12- and 10-bit resolution (see TABLE 4). The maximum carrier frequency can, in the same way, increase from: 5 to 10 kHz in the 16-bit mode, 7 to 14 kHz in the 14-bit mode, 11 to 32 kHz in the 12-bit mode, and 20 to 40 kHz in the 10-bit mode (see TABLE 5). The maximum tracking rate and carrier frequency for full performance are set by the power supply current control resistor (Rc) per the following tables: The carrier frequency should be 1/10, or less, of the sampling frequency in order to have many samples per carrier cycle. The converter will work with reduced quadrature rejection at a carrier frequency up to 1/4 the sampling frequency. Carrier frequency should be at least 3.5 times the BW in order to eliminate the chance of jitter.
REDUCED POWER SUPPLY CURRENTS
When Rs = 30 k (tracking rate is not being pushed), nominal power supply current can be cut from 14 to 9 mA by setting Rc = 53 k.
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RDC-19220 SERIES R-12/05-0
TABLE 4. MAX TRACKING RATE (MIN) IN RPS
RC&RSET ( )
30k**or open
TABLE 5. CARRIER FREQUENCY (MAX) IN KHZ
Depending on the resolution, select one of the values from this row, for use in converter max tracking rate formula. (See previous page for formula.)
RS&RCLK
RESOLUTION 10 12 14 72 16 18 1200 288
( ) 30k
RC&RSET () 30k** or open 23k 23k 23k
RS&RCLK
RESOLUTION 10 20 24 34 40 12 11 12 24 32 14 7 11 14 * 16 5 7 10 *
()
30k 30k 20k 15k
23k 23k
20k 15k
1200 432 108 27 * 576 * *
* Not recommended. ** The use of a high quality thin-film resistor will provide better temperature stability than leaving open. Note: RC "Rcurrent" = RSET RS "Rsample" = RCLK
* Not recommended. ** The use of a high quality thin-film resistor will provide better temperature stability than leaving open. Note: RC "Rcurrent" = RSET RS "Rsample" = RCLK
TABLE 6. TRANSFORMERS
P/N 52034 52035 52036 52037 52038 B-426 52039-X 24133-X TYPE S-R S-R R-R R-R R-R Reference Synchro Reference ANGLE LENGTH WIDTH FREQUENCY IN (VRMS)* OUT (VRMS)** ACCURACY*** (IN) (IN) (HZ)* 400 400 400 400 400 400 60 60 11.8 90 11.8 26 90 115 90 115 2 2 2 2 2 3.4 2 3/6 **** 1 1 1 1 1 N/A 1 N/A 0.81 0.81 0.81 0.81 0.81 0.81 1.1 1.125 0.61 0.61 0.61 0.61 0.61 0.61 1.14 1.125 HEIGHT (IN) 0.3 0.3 0.3 0.3 0.3 0.32 .42 .42 FIGURE NUMBER 5A 5A 5B 5B 5B 5C 5D 5D
NOTE 1 AVAILABLE FROM BETA BETA BETA BETA BETA BETA DDC DDC
* 10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances ** 2 Vrms Output Magnitudes are -2 Vrms 0.5% full scale *** Angle Accuracy (Max Minutes) **** 3 Vrms to ground or 6 Vrms differential (3% full scale) Dimensions are for each individual main and teaser 60 Hz Synchro transformers are active (requires 15 Vdc power supplies) 400 Hz transformer temperature range: -55C to +125C 60 Hz transformer (52039-X, 24133-X) temperature ranges: add to part number -1 or -3, -1 = -55C to +85C -3 = 0 to +70C
Note 1: Available from refer's to the company that the transformer is available from. Beta Transformer Technology Corporation www.bttc-beta.com
0.61 MAX (15.49) 0.61 MAX (15.49) 0.30 MAX (7.62) 0.09 MAX (2.29) 0.15 MAX (3.81) 0.15 MAX (3.81) 0.09 MAX (2.29)
0.30 MAX (7.62) 0.09 MAX (2.29) 0.61 MAX (15.49) 0.15 MAX (3.81) 0.15 MAX (3.81)
0.61 MAX (15.49) 0.09 MAX (2.29)
1
345 T1A
11 12 T1B
14 15
0.81 MAX (20.57) 0.600 (15.24) 0.115 MAX (2.92)
1
345 T1A
11 12 T1B
14 15
0.81 MAX (20.57) 0.600 (15.24) 0.115 MAX (2.92)
10 9 8 7 6
20 19 18 17 16
10 9 8 7 6
20 19 18 17 16
SIDE VIEW TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER PLATED BRASS Dimensions are shown in inches (mm).
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
SIDE VIEW TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER PLATED BRASS Dimensions are shown in inches (mm).
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
T1A S1 1 5 S3 SYNCHRO INPUT T1B 11 16 -COS 3 10 +SIN RESOLVER OUTPUT
RESOLVER INPUT S3 3
T1A
6
-SIN
S1
1
6
-SIN
10
+SIN RESOLVER OUTPUT
T1B S4 11 16 -COS
S2
15
20
+COS
S2
15
20
+COS
FIGURE 5A. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
FIGURE 5B. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
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RDC-19220 SERIES R-12/05-0
CASE IS BLACK AND NON-CONDUCTIVE 1.14 MAX (28.96) 0.25 (6.35) MIN.
*
S3
*
S1
*
+15 V (+15 V)
*
+S (-R)
+
0.32 MAX (8.13)
0.61 MAX (15.49) 0.125 MIN (3.17) 0.09 MAX (2.29) 0.15 MAX (3.81)
1.14 MAX (28.96)
*
*
* *
52039 or 24133
0.85 0.010 (21.59 0.25)
123 T1A
5 0.600 0.81 MAX (15.24) (20.57)
(RH) S2 (RL) +
*
*
(V) V
(+R) +C
(-Vs) -Vs
*
*
*
0.13 0.03 (3.30 0.76)
10 9 8 7 6 0.105 (2.66)
SIDE VIEW TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER-PLATED BRASS Dimensions are shown in inches (mm).
(BOTTOM VIEW)
0.42 (10.67) MAX.
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW
0.175 0.010 (4.45 0.25) NONCUMULATIVE TOLERANCE
0.21 0.3 (5.33 0.76) 0.040 0.002 DIA. PIN. SOLDER PLATED BRASS
+15 V
+15 V
Input
1 INPUT 5
6 OUTPUT 10
RH 24133 RL
Output +R (RH) -R (RL)
Input S1 S2 S3 52039
Output +S +C
V (Analog Gnd)
-Vs (-15 V)
V (Analog Gnd)
-Vs (-15 V)
The mechanical outline is the same for the synchro input transformer (52039) and the reference input transformer (24133), except for the pins. Pins for the reference transformer are shown in parenthesis ( ) below. An asterisk * indicates that the pin is omitted.
FIGURE 5C. TRANSFORMER LAYOUT AND SCHEMATIC (REFERENCE INPUT - B-426)
FIGURE 5D. 60 HZ SYNCHRO AND REFERENCE TRANSFORMER DIAGRAMS (SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)
EXTERNAL REFERENCE LO HI 1 5 B-426 6 10
RB CBW RV
CBW/10
-S RL RH S1 1 S3 3 S4 S2 11 TIB 15 16 52036(11.8V) OR 52037(26V) OR 52038(90V) TIA 6 20 +C -C COS AGND GND 10 +S
SIN
-R
+R
-VSUM
VEL -VCO DIGITAL OUTPUT
RDC-19220
16 CB BIT INH EM EL
30K
Rs A B +5V -5V
Rc
30K
OR SYNCHRO INPUT
RESOLUTION CONTROL S1 1 3 5 11 S2 15 TIB 10 TIA 6 20 +C AGND GND +S
}
RL
RH
S3
16 52034(11.8V) OR 52035(90V)
FIGURE 6. TYPICAL TRANSFORMER CONNECTIONS
Data Device Corporation www.ddc-web.com 9 RDC-19220 SERIES R-12/05-0
TYPICAL INPUT CONNECTIONS
FIGURES 7 through 9 illustrate typical input configurations
EXTERNAL REF LO HI
R1 R3
R2 R4
S3 10k (1%)
+S -S SIN COS -C
10k (1%)
-R
+R
S1
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
+C A GND GND
S4
S2
RESOLVER
Notes: 1) Resistors selected to limit Vref peak to between 1 V and 5 V. 2) External reference LO is grounded, then R3 and R4 are not needed, and -R is connected to GND. 3) See thin film network DDC-55688-1.
FIGURE 7A. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
S3
R1
+S
-S
SIN
R2
S1
S2
R1 R2
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
+C
S4
A GND -C
2 R2 = R1 + R2 X Volt R1 + R2 should not load the Resolver too much; it is recommended to use a R2 = 10k.
COS
R1 + R2 Ratio Errors will result in Angular Errors, 2 cycle, 0.1% Ratio Error = 0.029 Peak Error.
FIGURE 7B. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
Data Device Corporation www.ddc-web.com 10 RDC-19220 SERIES R-12/05-0
SIN
S1 S3
Ri Ri
Rf
-S +S +
Rf
RESOLVER INPUT A GND COS
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
S4 S2
Ri Ri
8 10
Rf
-C +C +
Rf
CONVERTER
Ri x 2 Vrms = Resolver L-L rms voltage Rf Rf 6 k S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter. Note : For 2V direct input use 10k matched resistors for Ri & Rf.
FIGURE 8A. DIFFERENTIAL RESOLVER INPUT
SIN 3 S1 S3 1 6
Ri Ri
Rf
-S 2 +S 5 +
Rf
RESOLVER INPUT A GND 4 COS 13
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
S4 S2
16 7
Ri Ri
8 10
Rf
-C 15 +C +
Rf
12 CONVERTER
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter. For DDC-49530 or DDC-57470: Ri = 70.8 k, 11.8 V input, synchro or resolver. For DDC-49590: Ri = 270 k, 90 V input, synchro or resolver. Maximum addition error is 1 minute using recommended thin film package. Note on DC Offset Gains: Input options affect DC offset gains and therefore affect carrier frequency ripple and jitter. Offsets gains associated with differential mode, (offset gain for differential configuration = 1 + RF/RI) and direct mode (offset gain for direct configuration = 1), show differential will always be higher. Higher DC offsets cause higher carrier frequency ripple due to demodulation process. This carrier frequency ripple because it is riding on the top of the DC error signal causes jitter. A higher carrier frequency vs bandwidth ratio will help decrease ripple and jitter associated with offsets. Summary: R/D's with differential inputs are more susceptible to offset problems than R/D's in single ended mode. RD's in higher resolutions, such as 16 bit, will further compound offset issues due to higher internal voltage gains. Although the differential configuration has a higher DC offset gain, the differential configuration's common mode noise rejection makes it the preferred input option. The tradeoffs should be considered on a design to design basis. Also refer to FAQ-GIQ-021.
FIGURE 8B. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530, DDC-57470 (11.8 V), DDC-73089 (2V), OR DDC-49590 (90 V)
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SIN
S1 S3
Ri Ri
Rf
-S +S +
Rf
A GND COS
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
Ri Ri Ri /2 Rf / 3
CONVERTER
Ri x 2 Vrms = Synchro L-L rms voltage Rf Rf 6 k S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the converter.
Rf / 3
-C +C +
S2
FIGURE 9A. SYNCHRO INPUT
SIN 3 S1 S3 1 6
Ri Ri
Rf
-S 2 +S 5 +
Note: The five external BW components as shown in FIGURE 1 and 2 are necessary for the R/D to function.
Rf
A GND 4 COS 14
16 7 9
Ri Ri Ri /2
8 15
Rf / 3
-C 15 +C 10 Rf / 3 11 +
S2
CONVERTER
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the converter. 90 V input = DDC-49590: Ri = 270 k, 90 V input, synchro or resolver. 11.8 V input = DDC-49530 or DDC-57470: Ri = 70.8 k, 11.8 V input, synchro or resolver. Maximum addition error is 1 minute.
FIGURE 9B. SYNCHRO INPUT, USING DDC-49530/DDC-57470 (11.8 V), DDC-73089 (2V) OR DDC-49590 (90 V)
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tor to an inverting integrator with a 50 pF nominal feedback capacitor. When it integrates to -1.25 V, the converter counts up 1 LSB and when it integrates to +1.25 V, the converter counts down 1 LSB. When a count is taken, a charge is dumped on the capaci
Magnitude of Error is in radians Quadrature Voltage is in volts Full Scale signal is in volts = signal to REF phase shift An example of the magnitude of error is as follows: Let: Quadrature Voltage = 11.8 mV Let: F.S. signal = 11.8 V Let: = 6 Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit. Note: Quadrature is composed of static quadrature which is specified by the synchro or resolver supplier plus the speed voltage which is determined by the following formula: Speed Voltage = (rotational speed/carrier frequency) * F.S. signal Where:
VELOCITY TRIMMING
RDC-19220 Series specifications for velocity scaling, reversal error and offset are contained in TABLE 1. Velocity scaling and offset are externally trimmable for applications requiring tighter specifications than those available from the standard unit. FIGURE 10 shows the setup for trimming these parameters with external pots. It should also be noted that when the resolution is changed, VEL scaling is also changed. Since the VEL output is from an integrator with capacitor feedback, the VEL voltage cannot change instantaneously. Therefore, when changing resolution while moving there will be a transient with a magnitude proportional to the velocity and a duration determined by the converter bandwidth.
INCREASED TRACKING/DECREASED SETTLING (GEAR SHIFTING)
Connecting the BIT output to the resolution control lines (A and B) will change the resolution of the converter down ("gear shift") and make the converter settle faster and track at higher rates. The converter bandwidth is independent of the resolution.
Speed Voltage is the quadrature due to rotation. Rotation speed is the rps (rotations per second) of the synchro or resolver. Carrier frequency is the REF in Hz.
PHASE SHIFT COMPENSATION ADDITIONAL ERROR SOURCES
Quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. This voltage is due to capacitive or inductive coupling in the synchro or resolver signals. A digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. The magnitude of this error is given in the following formula: Magnitude of Error = (Quadrature Voltage/F.S.signal) * tan Where:
RDC-19220
C + REF R - REF - REF + REF
FIGURE 11 illustrates a circuit to LEAD or LAG the reference into the converter that will compensate for phase-shift between
LAG R C - REF - REF
+ REF
+ REF
LEAD
tan =
+5 V
Xc
R
100 RV
100 k (OFFSET) -5 V
Where = desired phase-shift 1
-VCO
0.8 R V
Xc =
2fc
0.4 RV (SCALING)
VEL
Where f = carrier frequency Where c = capacitance
FIGURE 10. VELOCITY TRIMMING
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FIGURE 11. PHASE-SHIFT COMPENSATION
RDC-19220 SERIES R-12/05-0
the signal and the reference to reduce the effects of the quadrature. This should be used for greater than 6 phase shift between Ref and COS/SIN inputs.
LVDT MODE
As shown in TABLE 1 the RDC-19220 Series units can be made to operate as LVDT-to-digital converters by connecting Resolution Control inputs A and B to "0," "1," or the -5 volt supply. In this mode the RDC-19220 Series functions as a ratiometric tracking linear converter. When linear ac inputs are applied from a LVDT the converter operates over one quarter of its range. This results in two less bits of resolution for LVDT mode than are provided in resolver mode. FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some LDVT output signals will need to be scaled to be compatible with the converter input. FIGURE 12C is a schematic of an input scaling circuit applicable to 3-wire LVDTs. The value of the scaling constant "a" is selected to provide an input of 2 Vrms at full stroke
of the LVDT. The value of scaling constant "b" is selected to provide an input of 1 Vrms at null of the LVDT. Suggested components for implementing the input scaling circuit are a quad opamp, such as a 4741 type, and precision film resistors of 0.1% tolerance. FIGURE 12A illustrates a 2-wire LVDT configuration. Data output of the RDC-19220 Series is Binary Coded in LVDT mode. The most negative stroke of the LVDT is represented by all zeros and the most positive stroke of the LVDT is represented by all ones. The most significant 2 bits (2 MSBs) may be used
TABLE 7. LVDT OUTPUT CODE (14-BIT R/D OR 12-BIT LVDT)
LVDT OUTPUT + over full travel + full travel -1 LSB +0.5 travel +1 LSB null - 1 LSB -0.5 travel - full travel - over full travel
Note: TABLE 7 refers to FIGURE 12C.
aR
OVER RANGE 01 00 00 00 00 00 00 00 11
MSB DATA xxxx 1111 1100 1000 1000 0111 0100 0000 xxxx xxxx 1111 0000 0000 0000 1111 0000 0000 xxxx
LSB
C1 SIN aR
xxxx 1111 0000 0001 0000 1111 0000 0000 xxxx
2 WIRE LVDT REF IN
R R
-S -
R
+
+S
FS = 2 V
C2
aR
VB
COS
R R
SIN + aR bR 2R' R' COS -C -S
FS=2V
R' R'
bR
R
+S
R 2R
R R + -C
REF
R
2R 2V R
+C
R VA R/2
+REF -REF
+ bR
bR
-2V
2R'
R' +C +REF -REF
C1 = C2, set for phase lag = phase lead through the LVDT.
FIGURE 12A. 2-WIRE LVDT DIRECT INPUT
Notes; 1. R 10k 2. Consideration for the value of R is LVDT loading. 3. RMS values given. 4. Use the absolute values of Va and Vb when subtracting per the formula for calculating resistance values, and then use the calculated sign of "Va and Vb" for calculating SIN and COS. The calculations shown are based upon full scale travel being to the Va side of the LVDT. 5. See the RDC application manual for calculation examples. 6. Negative voltages are 180 phase for the reference.
+S A GND -REF +REF +C
-S
SIN
b= 1 =1 VAnull VBnull
RDC-19220
LVDT OUTPUT VA
a=
2 (VA - VB )max. a (V - VB ) 2A
RDC-19220 INPUT 2V SIN 1V COS -FS NULL +FS
SIN=-1V+
-C
COS
VB +FS NULL -FS
a COS=-1V - (VA - VB ) 2
FIGURE 12B. 3-WIRE LVDT DIRECT INPUT
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FIGURE 12C. 3-WIRE LVDT SCALING CIRCUIT
RDC-19220 SERIES R-12/05-0
as overrange indicators. Positive overrange is indicated by code "01" and negative overrange is indicated by code "11" (see TABLE 7).
the timing to CB "Figure 15" before setting the INH latch. Therefore, there is no need to monitor the CB line when applying an inhibit signal to the converter.
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle in the transparent output data latch while data is being transferred. Application of an Inhibit signal does not interfere with the continuous tracking of the converter. As shown in FIGURE 13, angular output data is valid 300 ns maximum after the application of the negative inhibit pulse. Output angle data is enabled onto the tri-state data bus in two bytes. Enable MSBs (EM) is used for the most significant 8 bits and Enable LSBs (EL) is used for the least significant 8 bits. As shown in FIGURE 14, output data is valid 150 ns maximum after the application of a negative enable pulse. The tri-state data bus returns to the high impedance state 100 ns maximum after the rising edge of the enable signal. The Converter Busy (CB) signal indicates that the tracking converter output angle is changing 1 LSB. As shown in FIGURE 15, output data is valid 50 ns maximum after the middle of the CB pulse. CB pulse width is 1/(40 x Fs), which is nominally 375 ns. Note: The converter INH may be applied regardless of the CB line state. If the CB is busy the converter INH will wait for
BUILT-IN-TEST (BIT)
The Built-ln-Test output (BIT) monitors the level of error from the demodulator. This signal is the difference in the input and output angles and ideally should be zero. However, if it exceeds approximately 100 LSBs (of the selected resolution) the logic level at BIT will change from a logic 1 to a logic 0. A 500ms delay occurs before the excessive error bit becomes active. The dynamic delay is responsive to the active filler loop. This condition will occur during a large step and reset after the converter settles out. BIT will also change to logic 0 for an overvelocity condition, because the converter loop cannot maintain input/output or if the converter malfunctions where it cannot maintain the loop at a null. BIT will also be set low for a detected total Loss-of-Signal (LOS). The BIT signal may pulse during certain error conditions (i.e., converter spin around or signal amplitude on threshold of LOS). LOS will be detected if both sin and cos input voltages are less than 800 mV peak. The LOS has a filter on it to filter out the reference. Since the lowest specified frequency is 47hz (-27ms) the filter must have a time constant long enough to filter this out. Time constants of 50ms or more are possible.
INHIBIT
300 ns max
ENCODER EMULATION
The RDC-19220 series can be made to emulate incremental optical encoder output signals, where such an interface is desired. This is accomplished by tying EL to -5 V, whereby CB becomes Zero Index (Zl) Logic 1 at all 0s, the LSB+1 becomes A, and the exclusive-or of the LSB and LSB+1 becomes B emulating A QUAD B signals as illustrated in FIGURE 16A. Also, the LSB byte is always enabled.
DATA
DATA VALID
FIGURE 13. INHIBIT TIMING
ENABLE
1/ (40 x FS ) (375 nsec nominal)
150 ns MAX 100 ns MAX DATA HIGH Z DATA VALID HIGH Z
CB
*
50 ns DATA VALID DATA VALID
Note: For 16 BIT BUS operation, EM/EL may be tied to ground for transparent mode, as long as only 1 R/D channel is on the data bus.
DATA
* Next CB pulse cannot occur for a minimum of 150 nsec.
FIGURE 14. ENABLE TIMING
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FIGURE 15. CONVERTER BUSY TIMING
RDC-19220 SERIES R-12/05-0
CB (ZI) LSB +1
(ZI) A B
LSB EL -5 V
FIGURE 16A. INCREMENTAL ENCODER EMULATION
R2 2k RDC-19220 C2 220 pF
13 12
U2D 74AC86 11 A
LSB +1 LSB
2 1
U2A 74AC86 3
R1 2k C1 220 pF
4 5
U2B 74AC86 6 B
R3 2k CB/NRP EL D1 1N4148 -5 V NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL COMPATIBLE LOGIC WILL SKEW THE DELAYS. C3 120 pF
9 10
U2C 74AC86 8 NRP
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
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16
RDC-19220 SERIES R-12/05-0
TYPICAL -5 VOLT CIRCUITS
Since the 40-pin DDIP RDC-19220 does not have a pinout for the -5 V inverter, it may be necessary to create a -5 V from other supplies on the board. FIGURE 17 illustrates several possibilities.
TABLE 9. RDC-19222 PINOUTS (44-PIN, +5 V ONLY)
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.1 V ZENER
NAME EL +5 V A B INH +REF -REF -VCO -VSUM VEL +C COS -C +S SIN -S -5 V RS RC EM A GND -5C (-5 V)
# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 -CAP GND +CAP
NAME
PINOUT FUNCTION TABLES BY MODEL NUMBER
TABLES 8 ,9, and 10 detail pinout functions by the DDC model number.
-15 79LO5 -5
+5C (+5V) BIT CB Bit 1 (MSB) Bit 9 Bit 2 Bit 10 Bit 3 Bit 11 Bit 4 Bit 12 Bit 5 Bit 13 Bit 6 Bit 14 Bit 7 Bit 15 Bit 8 Bit 16 (LSB)
3 TERMINAL NEGATIVE REGULATOR -5
-15 10.2 V ZENER
-5
15 16 17 18 19 20 21 22
-12 6.8 V ZENER
-5
-15
FIGURE 17. TYPICAL -5 VOLT CIRCUITS TABLE 8. RDC-19220 PINOUTS (40-PIN)
# 1 2 3 4 5 6 7 8 9 NAME A B INH +REF -REF -VCO -VSUM VEL +C DESCRIPTION # NAME DESCRIPTION Power Supply Enable LSBs (see note) LSB Resolution Control 40 +5 V Resolution Control 39 EL Inhibit +Reference Input -Reference Input Neg VCO Input Vel Sum Point Velocity Output Signal Input Signal Output Signal Input Signal Input Signal Output Signal Input Power Supply Sampling Set Current Set Enable MSBs Analog Ground Ground 38 Bit 16 37 Bit 8 36 Bit 15 35 Bit 7 34 Bit 14 33 Bit 6 32 Bit 13 31 Bit 5 30 Bit 12 29 Bit 4 28 Bit 11 27 Bit 3 26 Bit 10 25 Bit 2 24 Bit 9 23 Bit 1 22 CB 21 BIT MSB Converter Busy Built-In-Test
TABLE 10. RDC-19224 PINOUTS (44-PIN)
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 -REF -VCO -VSUM VEL +C COS -C +S SIN -S -5V RS RC EM A GND -5C (-5V) -CAP GND +CAP +5C (+5V) BIT CB NAME # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 BIT 9 BIT 2 BIT 10 BIT 3 BIT 11 BIT 4 BIT12 BIT 5 BIT13 BIT 6 BIT 14 BIT 7 BIT 15 BIT 8 BIT 16 (LSB) EL +5V A B INH +REF NAME BIT 1 (MSB)
10 COS 11 -C 12 +S 13 +SIN 14 -S 15 -5 V 16 RS 17 RC 18 EM 19 A GND 20 GND
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17
RDC-19220 SERIES R-12/05-0
PIN NUMBERS FOR REF ONLY 0.125 0.020 (3.18 0.508) 0.050 0.010 (1.27 0.25)
0.590 0.010 (14.99 0.25) 1 40
0.115 0.010 (2.921 0.25)
0.100 0.010 TYP (2.54 0.25)
2.000 0.020 (50.8 0.51)
0.018 0.006 TYP (0.46 0.15)
0.050 0.020 TYP (1.27 0.51)
20
21 0.012 0.004 TYP (0.31 0.10)
DIMENSIONS SHOWN ARE IN INCHES (MM).
0.095 0.010 (2.41 0.25)
0.600 - 0.020 (15.25 - 0.51 )
+1.27
+0.050
FIGURE 18. RDC-19220 (40-PIN DDIP) CERAMIC PACKAGE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com
18
RDC-19220 SERIES R-12/05-0
PIN #'S SHOWN FOR REFERENCE ONLY
PIN 1 IDENTIFIER ALTERNATE PIN 1 IDENTIFIER
6
40
0.690 SQ. .005 (17.53) 0.650 SQ. NOM (16.51)
C LC P
D UE IN .155 MAX (3.94) NT O SC DI
05 20 3, Q
.020 MIN
.620 SQ .010 (15.75) .016 .005 (.41)
DIMENSIONS SHOWN ARE IN INCHES (MM) TOLERANCE IN INCHES
0.010 x 45 CHFR (3) (0.25)
.050 .002 (1.27)
FIGURE 19. RDC-19222 (44-PIN PLASTIC J-LEAD) MECHANICAL OUTLINE
0.075 0.010 (1.91 0.25) 0.500 0.010 (12.70 0.25) 0.050 TYP (1.27)
6 7 1 40 39
0.020 x 45 (0.51) CHAMFER (ORIENTATION MARK)
0.040 x 45 CHAMFER (1.02) (3 PLACES) 0.095 0.007 (2.413 0.18)
0.143 10 (REF) (3.63)
0.630 0.020 TYP (16.00 0.51) 0.500 0.010 (12.70 0.25)
0.017 TYP (0.43)
17 18 28 29
0.075 0.010 (1.91 0.25)
PIN NUMBERS FOR REF ONLY
0.650 SQ 0.010 (16.51 0.25) 0.690 0.010 TYP (17.53 0.25)
DIMENSIONS SHOWN ARE IN INCHES (MM)
FIGURE 20. RDC-19222 (44-PIN CERAMIC J-LEAD) MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com 19 RDC-19220 SERIES R-12/05-0
D
D1
E
E1
c
b
TOP VIEW
0.012 R (TYP) (0.30) A2 A .009 (0.23) MAX .005 (0.13) MIN 0.008 R (TYP) (0.20) DIMENSIONS ARE IN INCHES (MM)
A1
L
A INCHES .092 MAX 2.35 MAX
A1 0.0039 0.0098 MIN .10 MIN MAX .25 MAX
A2 .078 + .004 - .002 2.00 + .10 - .05
D
D1
E
E1
L .035 + .006 - .004 .88 + .15 - .10
c
b
.394 .520 .010 .004 13.20 10.00 .25 .10
.520 .394 .010 .004 13.20 10.00 .10 .25
.0315 .0138 BSC +.0020 .80 BSC .35 +.05
MM
FIGURE 21. RDC-19224 (44-PIN PLASTIC MQFP) MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com
20
RDC-19220 SERIES R-12/05-0
ORDERING INFORMATION
RDC-1922X-XXXX (Ceramic Package) Supplemental Process Requirements: T = Tape and Reel (Not available in 40-pin DDIP package) S = Pre-Cap Source Inspection L = 100% Pull Test Q = Pre-Cap Source and 100% Pull Test K = One Lot Date Code W = One Lot Date Code and Pre-Cap Source Inspection Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, Pre-Cap Source Inspection and 100% Pull Test Blank = None of the Above Accuracy: 2= 4 minutes + 1 LSB 3 = 2 minutes + 1 LSB Process Requirements: 0 = Standard DDC Processing, without Burn-In 1 = MIL-PRF-38534 Compliant 2 = Standard DDC Processing, with Burn-In 3 = MIL-PRF-38534 Compliant, with PIND testing 4 = MIL-PRF-38534 Compliant, with Solder Dip (Not available in lead free.)(Note 4) 5 = MIL-PRF-38534 Compliant, with PIND testing, and Solder Dip (Not available in lead free.)(Note 4) 6 = Standard DDC Processing, with PIND testing, and Burn-In 7 = Standard DDC Processing, with Solder Dip, and Burn-In (Not available in lead free.)(Note 4) 9 = Standard DDC Processing, with Solder Dip, without Burn-In (Not available in lead free.)(Note 4) Temperature Grade / Data Requirements: 1 = -55 to +125C 4 = -55 to +125C, with Variables Test Data Package: (Lead Free) (Note 3) 0 = 40-Pin DDIP, ("+5 volt only" power supply feature - not available) 2 = 44-Pin J-Lead
STANDARD DDC PROCESSING FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
TEST INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN MIL-STD-883 METHOD(S) 2009, 2010, 2017, and 2032 1014 1010 2001 1015 (note 1), 1030 (note 2) CONDITION(S) -- A and C C 3000g TABLE 1
Notes: 1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MIL- STD-883, Test Method 1015, Paragraph 3.2. Contact factory for details. 2. When applicable. 3. Consult factory for lead-time of lead free product. 4. Solder dip options contain tin-lead solder finish as applicable to solder dip requirements.
External Component Selection Software (refer to General Setup Conditions section) can be downloaded from DDC's web site: www.ddc-web.com. Data Device Corporation www.ddc-web.com RDC-19220 SERIES R-12/05-0
21
ORDERING INFORMATION
RDC-19224_ -XXXX (Plastic Package:) Supplemental Process Requirements: T = Tape and Reel (Note 2) Blank = None of the Above Accuracy: 2 = 4 minutes + 1 LSB 3 = 2 minutes + 1 LSB Process Requirements: 0 = No Burn-In 9 = Solder Dip, without Burn-In (Note 3) Temperature Grade: 2 = -40 to +85C 3 = 0 to +70C A = -40 to +125C Package Options: (Note 1) Blank = Standard G = Lead free Package Type: 2 = PLCC 44-Pin J-Lead (Discontinued Q3, 2005) 4 = MQFP 44-Pin (Available January 3, 2006)
Note 1: The lead-free option is available with a Matte Tin finish. DDC can provide the reliability and tin whisker growth data associated with these products ; however, tin whisker growth is dependent on the application enviornment and customers should collect their own reliability data and perform a risk assesment based on their individual requirements. Note 2: DDC does not recommend Tape and Reel due to potential lead damage. Note 3: Solder DIP is not available on the MQFP package.
THIN FILM RESISTOR NETWORKS FOR MOTION FEEDBACK PRODUCTS
Description DDC converters such as the RDC-19220 series require closely matched 2Vrms Sin/Cos input voltages to minimize digital error. DDC has custom thin film resistor networks that provide the correctly matched 2Vrms converter outputs for 11.8Vrms Resolver/Synchro or 90Vrms synchro applications. Any imbalance of the resistance ratio between the Sin/Cos inputs will create errors in the digital output. DDC's custom thin film resistor networks have very low imbalance percentages. The networks are matched to 0.02%, which equates to 1LSB of error for a 16-bit application.
THIN FILM RESISTOR NETWORK DDC-55688-1 DDC-49530 DDC-57470 DDC-49590 DDC-73089 DDC-57471 INPUT VOLTAGE (VRMS) 2 Single Ended 11.8 11.8 90 2 Differential 90 OUTPUT VOLTAGE (VRMS) 2 2 2 2 2 2 PACKAGE TYPE Ceramic DIP Plastic DIP Surface Mount Ceramic DIP Surface Mount Surface Mount
Note: For thin film network specifications see the "Thin Film Network Specifications for Motion Feedback Products" Data Sheet available from the DDC website. (Operating Temperature Range : -55 to +125C)
Data Device Corporation www.ddc-web.com
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RDC-19220 SERIES R-12/05-0
The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7771 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0) 89-150012-11, Fax: +49-(0) 89-150012-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
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DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2000 FILE NO. A5976
R-12/05-0
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PRINTED IN THE U.S.A.
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